Common Synthesis Issues

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Improper Generic Logic Optimization (syn_generic)

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Issue

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Reasons

1. None of the outputs in the top module are being driven.
2. Integrated clock-gating (ICG) cells are set to dont_use and dont_touch, even though they are loaded.
3. Valid flip-flop cells are not available because *dff* cells are set to dont_use and dont_touch.

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Solution for ICG cells

set_db [get_db base_cells *ICG*] .dont_use true
set_db [get_db base_cells *ICG*] .dont_touch true

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Solution for flip-flop cells

set_db [get_db base_cells *dff*] .dont_use true
set_db [get_db base_cells *dff*] .dont_touch true