> ## Documentation Index
> Fetch the complete documentation index at: https://blog.sumathi.dev/llms.txt
> Use this file to discover all available pages before exploring further.

# Common Synthesis Issues

## Improper Generic Logic Optimization (`syn_generic`)

### Issue

Generic logic optimization during `syn_generic` does not proceed as expected.

### Reasons

1. None of the outputs in the top module are being driven.
2. Integrated clock-gating (ICG) cells are set to `dont_use` and `dont_touch`, even though they are loaded.
3. Valid flip-flop cells are not available because `*dff*` cells are set to `dont_use` and `dont_touch`.

### Solution for ICG cells

```tcl theme={null}
set_db [get_db base_cells *ICG*] .dont_use true
set_db [get_db base_cells *ICG*] .dont_touch true
```

### Solution for flip-flop cells

```tcl theme={null}
set_db [get_db base_cells *dff*] .dont_use true
set_db [get_db base_cells *dff*] .dont_touch true
```


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