Inputs

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Netlist

• Contains ports, functionality, nets, and modules

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Constraints

• Clock-related information
• Design rule violation, transition, and capacitance specifications

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LEF (Library Exchange Format)

• Contains physical overview
• Cell names, sizes, and shapes of cells and macros

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LIB (Library)

• Timing view
• Delays at input and output pins of standard cells
• Capacitance and transition characteristics

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TF (Technology File)

• Technology file containing:
  • Resistance and capacitance of each metal layer
  • Spacing rules and colors of each metal layer
• Interconnect file:
  • Parasitic information of metal layers to generate SPEF
  • Mapping file to map with technology file

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Macro Library

• Contains macro cell definitions and specifications

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DEF (Design Exchange Format)

• Physical partition information
• Port details
• Complete design specifications